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Friday, June 22, 2012

Design Reuse: Fact or Fiction?

Design Reuse: Fact or Fiction?


When ordinary people think of the word "reuse," they immediately think of using an item for a different purpose than what it was originally designed for. An example of this could be a newspaper being used to protect a floor while someone is painting a wall. 

When the term "reuse technology" is used in the electrical engineering environment it takes on a completely different meaning. When engineers use the term reuse technology, they describe a process of storing and reapplying electronic circuitry completed during the design phase so it can be reapplied in future designs. 



Figure 1: Electrical or logical reuse deals with reusing schematic representations in future designs.



This technology can come in the form of electrical reuse as well as physical reuse. Electrical design reuse is the selecting, storing, and recalling of electrical circuitry found in a schematic design. Electrical reuse elements can also be referred to as "logical reuse elements" as well. Figure 1 illustrates electrical, or logical, reuse.
Physical design reuse is the selecting, storing and recalling of physical data found in a printed circuit board design. Figure 2 depicts an example of physical reuse.

Unfortunately, it's been our experience that neither format is being widely utilized in today's PCB design environments. And many users of electronic CAD tools find themselves still doing things the same old-fashioned way, being slow to adopt any new technologies regardless of their obvious benefits.




Figure 2: Physical reuse refers to reusing the actual PCB layout in future designs.


So instead of improving their current processes, these users just chug along, doing things the same old way and never realizing the advancements that can be realized in both productivity and accuracy.

When we take a closer look into the PCB engineering industry, we quickly find the reasons behind this resistance. Users are skeptical about utilizing new, unproven technologies that could - temporarily - keep them from achieving their immediate goal, a goal whose schedule is greatly affected by distractions large or small.

Design engineers are under extreme pressures to complete their tasks on time, and if they are forced to deviate from their normal activities to try some unproven process change - well, you get the idea. They are less apt to adopt any new process unless it can be proven to greatly improve their throughput and it requires little to no training to utilize.

Software vendors began experimenting with this reuse technology back in the late 1990s and early 2000s. The first attempt utilized more of a cut-and-paste approach, relying heavily on an ECO reconciliation process to resolve inconsistencies created during the cut-and-paste step. This methodology seemed to resolve some inconsistencies but was actually found to introduce problems with circuitry that were not involved with the newly added reuse. This was a major setback in design reuse adoption and set in motion a newer philosophy toward reuse building. Early adopters quickly realized that the reuse technology had not yet matured enough to make it useful in the designs of the time.

As time progressed, certain CAD software companies took the lead in reuse experimentation with the belief that with better algorithms they could yield better reuse results. These new algorithms expanded the compare capabilities so more data could be taken into consideration during the reuse generation process, hence yielding greater successes.

The expanded capabilities of the new algorithms came just in time, as more part-specific data was being introduced into the circuit board. With the introduction of component information systems (CIS) into the engineering flow, large quantities of component data was being infused into circuit boards to aid in the outputting of other required documentation. This additional data helped with the reuse rebuilding process because more unique data could be compared, helping to ensure a more precise reuse generation tool in the end.

Coupling component part data in the comparison was only the first leap in this technology. Comparing actual circuit board data also helped to ensure a better reuse process. Comparing board data, such as the number of layers, via types and layer types, all helped to ensure design data previously defined in a reuse would find itself located in exactly the same place when the reuse modules were reintroduced into a new design.

Reuse modules are created, stored, and reapplied using a variety of approaches. In the schematic environment, reuse data can be stored as separate circuits by selecting the electrical areas of choice followed by selecting the appropriate storage option. They can be recalled onto a new schematic sheet having the common reference designators automatically updated to a unique identifier. This automated process helps to eliminate any chance for duplicate reference designators, traditionally a major cause for reuse failure.

Design rules that were present on the schematic sheets are also maintained, and they are automatically set in the PCB CAD tool when the design data moves forward in the circuit board phase. Both of these actions can be completed once during the initial schematic reuse building phase, with the benefits recognized each time the reuse is applied to a new project.

Logical reuse can be set up in a hierarchical format as well. This usage model allows generation of both hierarchical symbols and lower-level circuitry, both of which are stored as library-type elements. This scheme provides easy access so the reusable elements can be quickly introduced to a new schematic by simply adding the single hierarchical symbol. The PCB-ready schematic sheet is automatically added as an additional sheet of data, complete with all the information previously generated and stored.


System Integration Considerations

Integration is also an important element that is available to engineers requiring reuse capabilities. When the schematic data is extracted and sent over to the circuit board design tool, integration can help ensure the proper PCB components are considered during the reuse building process. By selecting the reuse components defined on the schematic, you can guide the PCB reuse building process so only those selected parts are considered. This helps to ensure the proper discrete components required to recreate the reuse are the parts utilized. 

This methodology saves time and improves accuracy during the physical reuse building phase.
Physical reuse elements can be created, stored, and recalled using steps similar to those used when building logical reuse elements. The physical elements are usually derived from existing printed circuit board data (i.e., parts, connections/traces, via data and other data). Physical circuitry is designed as required, rules are set, attributes are defined, reuse data selected and stored on the hard drive as a reuse element. These physical reuse elements can be edited anytime, allowing for quick and efficient reuse modifications - all without having to redesign the reuse each time a modification is required.

Once created, physical reuse modules can be applied to designs using two methodologies. They can be added to designs that contain existing electrical information that originated from a schematic design, or they can be added as a completely new module regardless of the current electrical data contained in the PCB design.

Reuse modules being added to an existing design containing electrical information is the most common method of reuse. When a reuse is built from existing design data, all aspects of the stored reuse must be available in the design before the reuse can be accepted in the design. If the available design data is not a perfect match for the reuse content, then the reuse will not be applied and a detailed report reviewing the differences is presented to the designer.

Adding reuse modules using this method also does not require an ECO comparison process to reconcile difference generated during the adding process. This is primarily due to the advancements made in the core algorithms used to generate a new reuse. This advantage not only helps those with very sensitive schedule but also helps those that encountered errors during the building process.

Reuse applications can range from doing simple "golden circuit" generation to creating and storing user generated IP. Users are finding that some CAD vendor suppliers' reuse implementations are so good that they are able to store PCB-centric technologies like DDR and DDR II. Power supplies and fiber-optic channels can also qualify as true reuse candidates. Both logical and physical reuse would support both candidate types.

There are also some practical applications in the RF engineering world that reuse utilization can assist. Special geometries (antennas), when configured a special way, can be stored and recalled as combined reuse elements.

Customers whose schedules are very tight may find that design reuse provides them with the ability to design pieces of a circuit board layout design in parallel, allowing them to reduce their project design cycles by a significant amount. This is accomplished by simply dividing the circuit board into several sections and assigning each section to a PCB designer. The designer then completes that piece, builds a reuse from that circuit and then applies each of the reuse elements into one main design.

Design reuse, whether it's logical, physical or a combination of both, can significantly reduce project schedules, improve accuracy and provide peace of mind to users who are willing to take advantage of the technology available today. As the practical uses of design reuse increase, so will the advancements in reuse technology. Software providers such as Mentor Graphics will continue to support newer technological requirements as they become a part of the engineers' reality.

Todd Hendren is an applications engineer consultant for Mentor Graphics. He is a 20-year veteran in PCB design.

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